Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance

ABSTRACT

In a process for manufacturing a bipolar transistor, an intrinsic base is formed by a selective epitaxial growth while the lower surface of a base electrode single crystal silicon film 33 and the surface of a collector epitaxial layer 3 are exposed. In this process, the intrinsic base 8 and an extrinsic base 34 are grown as a single crystal to form a self-alignment type bipolar transistor having a reduced parasitic capacitance between the base and the collector.

This is a Continuation of application Ser. No. 08/361,993, filed on Dec.21, 1994 now abandoned.

FIELD OF THE INVENTION

This invention relates to a method for manufacturing a semiconductordevice, and particularly to a method for manufacturing a bipolar typesemiconductor device.

BACKGROUND OF THE INVENTION

A known bipolar type semiconductor device, a bipolar transistor, is asdisclosed in Japanese Patent Application Laid-open No. 4-330730.

FIG. 1 is a longitudinally-sectional view showing this conventionalsemiconductor device. In this semiconductor device, a high-concentrationN⁺ -type collector buried region 2 which contains arsenic as an impurityis selectively formed on a P⁻ -type single crystal silicon substrate 1having a resistivity of 10 to 20 Ωcm, and an N⁻ -type single crystalepitaxial layer 3 having an impurity concentration of 5×10¹⁵ cm⁻³ isformed at a thickness of 1.0 μm over the whole surface of the buriedregion 2. The epitaxial layer 3 is separated into a plurality of islandregions by oxide films 4 which are formed to extend to the substrate 1by a well-known selective oxidation method. In FIG. 1, only one islandregion 3 corresponding to the buried region 2 is illustrated. The islandtype region 3 is further separated into two parts by an oxide film 4'extending to the buried region 2. One part of the island region 3 at theleft side is designed to act as a collector region while the other partat the right side is designed to act as an N⁺ -type collector draw-outregion 5 and thus it is subjected to a phosphor diffusion treatment in asubsequent process to be highly doped. Through this process, a siliconsubstrate or body 100 is formed.

The substrate 100 is covered with a silicon nitride film 7, throughwhich an opening 101 for partially exposing the collector region 3 andfor forming a base and an opening 102 for exposing the collectordraw-out region 5 are formed. Preferably, a thin silicon oxide film isformed beneath the silicon nitride film 7.

A P⁺ -type polycrystalline silicon film 6 is selectively formed on thesilicon nitride film 7, and it is designed to horizontally extend fromthe edge of the opening 101 toward the center of the opening 101, and aP-type polycrystalline silicon film 9 is further formed on the lowersurface of the extended portion of the silicon film 6 toward thecollector region 3. In addition, a P-type base region 8 of singlecrystal silicon is formed on the exposed portion of the collector region3 by an epitaxial growth method, and the polycrystalline silicon film 9and the base region 8 contact each other.

Further, an N⁺ -type polycrystalline silicon layer 11 is formed at theopening 102 in contact with the collector draw-out region 5. The baseregion 8 and the polycrystalline silicon films 6 and 9 are covered withsilicon oxide films 13 and 14 except for an emitter forming portion. AnN-type emitter region 10 of single crystal silicon is formed on theexposed portion of the base region 8, and an emitter electrode 12-1, abase electrode 12-2 and a collector electrode 12-3 of aluminum areformed in contact with the emitter region 10, the polycrystallinesilicon film 6 and the polycrystalline silicon layer 11, respectively.This transistor is hereinafter referred to as the "first transistor".

In addition to the above publication, Japanese Patent Application No.4-322432 discloses a technique for crystallizing polycrystalline siliconfor a base electrode to obtain a single crystal silicon by a solid phaseepitaxial growth method.

Such a crystallizing technique as described above will be described indetail with reference to FIG. 2.

In this technique, a buried collector layer 2, an epitaxial layer 3 andan oxide film 110 are successively formed in this order on a Sisubstrate 1, and an opening 120 is formed through the oxide film 110.Subsequently, an amorphous SiGe film is formed on the exposed epitaxiallayer 3 and oxide film 110, and then it is replaced by a single crystalSiGe film 8 and a polycrystalline SiGe film 9 using the solid phaseepitaxial growth method. Thereafter, an emitter film 10 is formed on thesingle crystal SiGe film 8. This transistor is hereinafter referred toas the "second transistor". In FIG. 2, reference numerals 111, 112 eachdenote a silicon oxide film, 200 an emitter electrode, 201 a baseelectrode, 202 a collector electrode, 11 a collector film, 57 acollector wall layer, 54 a trench for element isolation, 55 a P⁺ -typelayer for channel cut, and 56 a silicon oxide film.

Through this process, the base-collector junction capacitance can bereduced, and the base layer and the base electrode draw-out layer can beformed in self-alignment.

However, the semiconductor devices as described above have the followingproblems.

With respect to the first transistor, when SiGe is grown as an intrinsicbase by a selective epitaxial growth method, the growth rate ofpolycrystalline SiGe is lower than that of single crystal SiGe(epitaxial SiGe). The difference in growth rate is dependent on theconcentration of Ge. For example, for Ge=10%, i.e. for Si₀.9 Ge₀.1, theratio of the polycrystalline SiGe growth rate to the epitaxial SiGegrowth rate (poly/epi growth rate ratio) is equal to 1/5 to 1/4.Therefore, when the thickness of the base region 8 is made thin enoughto maintain the necessary characteristics of the transistor, thethickness of the silicon nitride film 7 should be made thinner. As aresult, the distance between the polycrystalline silicon film 6 and thecollector region 3 is shortened, so that the parasitic capacitancebetween the base and the collector is increased.

With respect to the second transistor, the polycrystalline SeGedeposited in the same process is subjected to the solid phase epitaxialgrowth treatment to form the intrinsic base 8 and the base film 9.Accordingly, the thickness of the base film is substantially equal tothat of the intrinsic base. In order to improve a cut-off frequencyf_(T), the thickness of the intrinsic base must be reduced. However, inthis case the thickness of the base film is also reduced, resulting inincrease of a base resistance R_(b). That is, a trade-off is imposedbetween f_(T) and R_(b), so that the transistor cannot be improved inperformance as a whole.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicehaving high performance and reduced base-collector parasiticcapacitance, and in particular to provide a manufacturing method forsuch a semiconductor device.

In order to attain the above object, according to the present invention,there is provided a method for manufacturing a semiconductor device,comprising:

a first step of forming a first insulation film on the surface of afirst conduction type single crystal semiconductor layer;

a second step of forming on the first insulation film a first singlecrystal semiconductor film of a second conduction type through which afirst opening is selectively formed;

a third step of forming a second insulation film on the upper surface ofthe first single crystal semiconductor film and on the side surface ofthe first single crystal semiconductor film defining the first opening;

a fourth step of selectively removing the first insulation film usingthe second insulation film and the first single crystal semiconductorfilm as a mask to form through the first insulation film a secondopening which is larger than the first opening;

a fifth step of growing a second single crystal semiconductor film of asecond conduction type on the exposed surface of the sigle crystalsemiconductor layer within the second opening and growing a third singlecrystal semiconductor film of a second conduction type on the exposedlower surface of the first single crystal semiconductor film so that thesecond and third single crystal semiconductor films are connected toeach other; and

a sixth step of forming a third insulation film between the secondinsulation film and the second single crystal semiconductor film so asto cover the exposed side surface of the third single crystalsemiconductor film.

The single crystal semiconductor layer and the first to third singlecrystal semiconductor films may be made of silicon.

The single crystal semiconductor layer and the first single crystalsemiconductor film may be made of silicon, and the second and thirdsingle crystal semiconductor films may be made of silicon-germanium.

The first and third insulation films may be made of silicon oxide, andthe second insulation film may be made of silicon nitride.

A metallic silicide film may be formed on the first single crystalsemiconductor film in the second step.

In one feature of the present invention, a single crystal semiconductorof a first conduction type is formed on the surface of a semiconductorsubstrate, an area of the single crystal semiconductor being used as thesingle crystal semiconductor layer, and, in the second step, after athird opening is formed through the first single crystal semiconductorfilm at a portion corresponding to the other area of the single crystalsemiconductor, an amorphous semiconductor is deposited, then, by a solidphase epitaxial growth method using the single crystal semiconductor atthe other area in the third opening as a seed crystal, the amorphoussemiconductor is crystallized to a single crystal semiconductor, andthen a patterning of the crystallized single crystal semiconductor iscarried out to obtain the first single crystal semiconductor film.

The method may further comprise a seventh step of forming a fourthsingle crystal semiconductor film of a first conduction type on theexposed surfacre of the second single crystal semiconductor film afterthe sixth step. A polycrystalline silicon film may be formed on thefourth single crystal semiconductor film in the seventh step.

The method may further comprise a eighth step of forming apolycrystalline silicon film of a first conduction type on the exposedsurfacre of the second single crystal semiconductor film after the sixthstep and diffusing impurities of a first conduction type from thepolycrystalline silicon film to the second single crystal semiconductorfilm by heat treatment to form a first conduction type impuritydiffusion area.

According to the present invention, increase in the parasiticcapacitance between the base and the collector due to the difference inpoly/epi growth rate ratio at the selective epitaxial growth can besuppressed.

Further, according to the present invention, since the intrinsic baseand the base electrode silicon are formed in different steps, thetrade-off between f_(T) and R_(b) can be moderated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinally-sectional view showing a conventionalsemiconductor device;

FIG. 2 is a longitudinally-sectional view showing another conventionalsemiconductor device;

FIG. 3 is a longitudinally-sectional view showing a first embodiment ofa semiconductor device obtained according to the present invention;

FIGS. 4A to 4E are diagrams showing an essential steps of themanufacturing method according to the present invention;

FIG. 5 is a longitudinally-sectional view showing a second embodiment ofa semiconductor device obtained according to the present invention;

FIG. 6 is a longitudinally-sectional view showing a third embodiment ofa semiconductor device obtained according to the present invention;

FIG. 7 is a longitudinally-sectional view showing a fourth embodiment ofa semiconductor device obtained according to the present invention;

FIG. 8 is a longitudinally-sectional view showing a fifth embodiment ofa semiconductor device obtained according to the present invention;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments according to the present invention will bedescribed hereunder with reference to the accompanying drawings.

A first embodiment of the semiconductor device obtained by amanufacturing method according to the present invention will bedescribed with reference to FIG. 3.

An N⁺ -type collector buried region 2, into which, for example, arsenicions are selectively doped at a dose of 1×10¹⁶ cm⁻² and an energy of 70keV by an ion implantation, is formed on a P⁻ -type (100)-orientedsingle crystal silicon substrate 1 having a resistivity of 10 to 20 Ωcm.Boron ions are selectively doped at a dose of 1×10¹³ cm⁻² and an energyof 100 keV into a channel stopper buried region 31. An N⁻ -type singlecrystal epitaxial layer 3 having a phosphor concentration of about1×10¹⁶ cm⁻³ and a thickness of about 0.7 μm is formed over the wholesurface of the silicon substrate 1. The epitaxial layer 3 is separatedinto plural island regions by oxide films 4 which are formed to extendto the substrate 1 by the well-known selective oxidation method. In FIG.3, only a part of the epitaxial layer 3 corresponding to the buriedregion 2 is illustrated as an island region. The island region isfurther separated into two parts by the oxide film 4 extending to theburied regions 2 and 31. A part of the island region at the left side isdesigned to act as a collector region. The other part at the right sideis designed to act as an N⁺ -type collector draw-out region 5 and thusit is subjected to a phosphor ion implantation treatment in a subsequentprocess so as to be highly doped. Through this process, a substrate orbody 100 is formed.

The substrate 100 is covered with a silicon oxide film 32 of a thicknessof about 100 nm. The silicon oxide film 32 is designed so that anopening 101 for partially exposing the collector region 3 through thesilicon oxide film 32 and for forming a base and an opening 102 forexposing the collector draw-out region B are formed. A P⁺ -type singlecrystal silicon film 33, into which boron ions are doped at a dose of5×10¹⁵ cm⁻² and at an energy of 10 keV by the ion implantation, isselectively formed at a thickness of about 200 nm on the silicon oxidefilm 32, and the silicon film 33 is formed to extend from the edge ofthe opening 101 horizontally by about 200 nm. A P-type single crystalsilicon film layer 34 (about 50 nm in thickness, 6×10¹⁸ cm⁻³ of boronconcentration) is formed on the lower surface of the extended portion ofthe silicon film 33 toward the collector region 3. On the other hand, aP-type intrinsic base region 8 which is formed of single crystal siliconand has boron concentration of about 6×10¹⁸ cm⁻³ is formed at athickness of about 60 nm on the exposed portion of the collector region3, and the single crystal silicon film 34 and the intrinsic base region8 contacted one another.

The dimension of the extended portion of the silicon film 33 ispreferably larger than the thickness of the intrinsic base region 8.

An N-type single crystal silicon film 35 is formed at the opening 102 soas to contact the collector draw-out region 5. The base region 8 and thesingle crystal silicon films 33 and 34 are covered with a siliconnitride film 36 and a silicon oxide film 14 except for the emitterforming portion. Further, an N-type emitter region 10 of single crystalsilicon is formed at the exposed portion of the base region 8. Anemitter electrode 12-1, a base electrode 12-2 and a collector electrode12-3 which are formed of aluminum contact the emitter region 10, thesingle crystal silicon film 33 and the single crystal silicon film 35,respectively.

Next, essential steps of a method for manufacturing the semiconductordevice according to the present invention will be described withreference to FIGS. 4A to 4E. In the following description, only specificsteps which are different from the process as disclosed in the JapanesePatent Application Laid-open No. 4-330730 will be described.

First, referring to FIG. 4A, the whole surface of a P⁻ -type(100)-oriented silicon substrate 1 which has the resistivity of 10 to 20Ωcm is oxidized to form an oxide film having a thickness of about 6000Å, and a photoresist is patterned on the oxide film with a normallithography process. The SiO₂ film is selectively etched with HF-basedetchant using the photoresist as a mask to remove a portion of the SiO₂film which is not covered by the photoresist, and then the photoresistis removed.

In order to reduce the damage which will occur in a subsequent ionimplantation process and in order to form an alignment pattern used in asubsequent lithography process, the P⁻ -type Si substrate 1 which hasbeen subjected to the SiO₂ patterning treatment is oxidized to athickness of 500 Å in depth. Subsequently, ion implantation of As isperformed to selectively form an N⁺ -type buried region 2 only at theregion where the SiO₂ film of about 6000 Å as described above isremoved. An example of ion implantation condition is 70 keV and 5E15(5×10¹⁵) cm⁻². A heat treatment is conducted for three hours at atemperature of 1100° C. after the ion implantation. Through thisprocess, damage caused by the ion implantation is reduced and arsenicwhich is doped in order to reduce the collector resistance is diffused.Thereafter, the surface SiO₂ film on the substrate is removed from thewhole surface thereof with the HF-based etchant. In this process, ionimplantation is used. However, the same N⁺ -type buried layer may beformed by conducting the heat treatment on a film coated containingarsenic in high concentration to diffuse arsenic. Antimony Sb may beused as impurity.

Subsequently, a channel stopper P⁺ -type buried layer 31 is formed toprevent formation of an inversion layer on the P⁻ -type siliconsubstrate beneath the selective oxide film 4 which is formed for elementisolation. A condition for forming the layer 31 is, for example, asfollows: The surface of the substrate is oxidized by about 400 Å, andthereafter a photoresist is applied and left only on a predeterminedarea in a lithography process to conduct the ion implantation of boronusing the photoresist as a mask. An ion implantation condition is, forexample, 110 keV and 1E14 (1×10¹⁴) cm⁻². A heat treatment is conductedat 1000° C. under nitrogen atmosphere for one hour.

Subsequently, the oxide film on the surface of the substrate iscompletely removed with HF-based etchant, and then an N-type siliconepitaxial layer 3 is grown. SiH₄ or Si₂ H₂ Cl₂ is used as raw gas, PH₃is used as doping gas, and the growth temperature is set to 1000° to1100° C. Through this process, the epitaxial layer in which an area of1×10¹⁹ cm⁻³ or less in the impurity concentration is formed at athickness of about 0.7 μm and the average concentration from the surfaceto a transition region to the buried region is equal to about 1×10¹⁶cm⁻³.

Thereafter, an SiO₂ film is formed at a thickness of about 500 Å on thesurface, and a silicon nitride film is deposited on the surface of theSiO₂ film by the LPCVD method. At this time, the temperature is set to700° to 900° C. and a mixture of SiH₂ Cl₂ and NH₃ gases is used forreaction. A photoresist patterning treatment is conducted in thelithography process, and the silicon nitride film is etched by a dryetching method using the photoresist as a mask. If the dry etchingtreatment is finished at the time when the surface of the SiO₂ film ofabout 500 Å beneath the silicon nitride film is etched by about 100 to200Å, the silicon nitride film can be perfectly etched without damagingthe substrate side. Thereafter, the photoresist is removed. Theselective oxidation is carried out using the patterned silicon nitridefilm as a mask to form the selective oxide film 4. For example, when theselective oxidation is carried out at 1000° C. in steam for 4 hours, anoxide film of about 8000 Å in thickness can be formed.

Subsequently, the silicon nitride film which was used as the mask isperfectly removed by immersing in phosphoric acid H₃ PO at about 130° C.for one hour.

Thereafter, a silicon oxide film 32 is deposited at a thickness of about1000 Å on the surface of the substrate, and only the silicon oxide filmon an area where a collector electrode will be formed is subjected tothe lithography and the dry etching treatment to perform the patterningof the silicon oxide film 32. Thereafter, the ion implantation ofphosphor is performed at a dose of 5×10¹⁴ cm⁻² and at an energy of 70keV, and the heat treatment is conducted at a temperature of 900° C.under nitrogen atmosphere after the resist is removed. Subsequently,amorphous silicon 37 is deposited on the whole surface of the substrateat about 500° C. using Si₂ H₆ as raw gas. Through these processes, theintermediate product shown in FIG. 4A is obtained.

Subsequently, the amorphous silicon 37 is subjected to a heat treatment,for example a laser annealing treatment, to change the amorphous silicon37 into a single crystal silicon 38 in the solid phase epitaxial growthusing the single crystal silicon exposed at the opening 102 as a core orseed crystal. This is shown in FIG. 4B.

The single crystal silicon thus formed is patterned by the lithographyand the dry etching treatment, and then the photoresist is removed.

Next, the patterning treatment is conducted by the lithography so thatan opening is formed through the photoresist above the single crystalsilicon 33 for the base electrode, then the ion implantation is carriedout using the photoresist as a mask at 10 keV to dope boron at a dose of5×10¹⁵ cm⁻², and then the photoresist is removed. Through the sameprocess, phosphor is doped into the single crystal silicon 35 for thecollector electrode at a dose of 5×10¹⁴ cm⁻² and at an energy of 50 keV.Subsequently, the single crystal silicon at the region in which boron orphosphor is doped is annealed at 610° C. in a furnace. This is shown inFIG. 4C.

Thereafter, a silicon nitride film 36 is deposited at a thickness ofabout 2400 Å by a normal LPCVD method. Subsequently, the photoresist isapplied and made to form an opening at a portion thereof correspondingto an emitter region by the lithography, and the silicon nitride film 36and the single crystal silicon 33 are continuously etched using thephotoresist as a mask by an anisotropic dry etching treatment.Thereafter, the photoresist is removed, a silicon nitride film isdeposited on the surface thereof at a thickness of about 1200 Å by theLPCVD method, and then the insulating silicon nitride film is removed toa depth of about 1500 Å from the surface by the anisotropic dry etchingtreatment. Further, the silicon oxide film is side-etched laterally byabout 0.2 μm with HF-based etchant.

As a result, the upper surface of the N⁻ -type silicon epitaxial layer 3is exposed at only a portion thereof corresponding to a base region. Thesingle crystal silicon film 33 for base electrode is designed to projecthorizontally to the upper side of the base region. The distance from theend of the projection to the sidewall of the silicon oxide film 32 isset to about 2000 Å, and the lower surface of the projection is exposedby the length corresponding to the distance. This is shown in FIG. 4D.

Subsequently, a single crystal silicon film 8 containing P-typeimpurities is grown on the surface of the exposed epitaxial layer 3 asshown in FIG. 4E, and at the same time a single crystal silicon film 34containing P-type impurities is grown on the exposed lower surface ofthe single crystal silicon film 33. In order to perform the aboveprocess, the substrate is washed and immersed in HF-based etching agentfor a short time (for example, for 30 seconds in 130BHF) as apre-treatment to remove a natural oxide film, and then a wafer is placedin an ultra high vacuum/chemical vapor deposition (UHV/CVD) apparatus.Thereafter, the heat treatment is conducted on the wafer at 850° C. forabout 10 minutes in the apparatus to perfectly remove the residual ofthe natural oxide film which is imperfectly removed and thus remainseven through the above etching pre-treatment. If this heat treatment isinsufficient, a subsequent selective epitaxial growth tends to beimperfectly performed.

Subsequently, the base is grown by an UHV/CVD method. The base growthcondition is as follows: substrate temperature of 605° C., Si₂ H₆ flowrate of 12 sccm, pressure of about 5×10⁻⁴ Torr, selective growth ofsilicon film at a rate of 100 Å/min.

B₂ H₆ is used as doping gas to grow a P-type silicon film. The flow rateof B₂ H₆ is determined to obtain a predetermined P-type impurityconcentration. Under the above condition, an epitaxial film is grown toform an intrinsic base 8 having about 600 Å thickness and boronconcentration of 6×10¹⁸ cm⁻³. In this case, it is needless to say that asingle crystal silicon extrinsic base film 34 is also selectively grown.The selective growth as described above is continued until the intrinsicbase 8 and the single crystal silicon extrinsic base 34 are connected toeach other. FIG. 4E shows a state in which the intrinsic base 8 and theextrinsic base 34 are connected to each other.

Through this process, the growth of the intrinsic base 8 and theelectrical connection between the intrinsic base 8 and the singlecrystal silicon 33 can be simultaneously performed in one step. Thefinal thickness of the intrinsic base 8 is about 600 Å, and the finalthickness of the extrinsic base 34 is about 500 Å. The growth of thebase 8 may be performed using the LPCVD method for performing growthunder pressure of several Torrs, or other epitaxial growth methods suchas a molecular beam epitaxial method, etc.

Subsequently, a silicon oxide film 14 is deposited on the whole surfaceof the exposed portion by the LPCVD method, and then etched back by thedry etching treatment. The wafer is placed in the UHV/CVD apparatusagain for the treatment to leave the silicon oxide film 14 on the sidewalls of the extrinsic base 34 and the silicon nitride film 36.Subsequently, emitter single crystal silicon 10 is grown to a thicknessof about 1000 Å on a portion of the intrinsic base 8 which is coatedwith no insulation film while N-type impurities are doped in the growingemitter single crystal silicon 10 at a concentration of 1×10¹⁹ cm⁻³.

In a subsequent process, holes for metal electrodes of the base and thecollector are formed in the silicon nitride film 36, an aluminum film isdeposited on the whole surface, and then aluminum electrodes 12-1, 12-2and 12-3 remain at the emitter, base and collector portions respectivelyby the lithography. As a result, a semiconductor device shown in FIG. 3can be obtained.

The embodiment as described above relates to an NPN transistor, however,it can be applied to a PNP transistor by changing the type ofimpurities.

Next, a second embodiment will be described with reference to FIG. 5.

Referring to FIG. 5, in the semiconductor device of this embodiment, analloy film of silicon and germanium is formed using Si₂ H₆ and GeH₄ asraw gas when the base is grown by the UHV/CVD method. The same conditionof the first embodiment for forming the base is used in this embodiment,and as an additive condition, GeH₄ is added in the following flow rate:Si₂ H₆ :GeH₄ =3:2. With this addition, a single crystal silicongermanium alloy film 15 containing 10 mol % germanium is epitaxiallygrown on the collector 3.

Simultaneously with the growth of the alloy film 15, a single crystalsilicon germanium alloy extrinsic base 16 is also grown on the lowersurface of the overhang portion of the base electrode single crystalsilicon 33, and then it is connected to the intrinsic base film 15.

The forbidden band gap of the silicon germanium alloy base film 15becomes smaller than that of silicon which is used for the emitter. Thereduction amount is dependent on the mol percentage of Ge and the strainof the silicon germanium alloy film. The difference in forbidden bandgap acts as a barrier to minority carriers injected from the base to theemitter, so that increase of base current is suppressed. That is, thedifference in the forbidden band gap improves the cut-off frequencyf_(T). Further, even when the base layer is designed to be thinner andhighly doped to keep the break-down voltage BV_(CEO) between thecollector and the emitter to a predetermined value or more, thedifference in the forbidden band gap also enables a current gain to beset to a sufficiently high value.

In this embodiment, SiGe is used for the base, and the parasiticcapacitance formed between the collector epitaxial layer 3 and the baseelectrode single crystal silicon film 33 is reduced because the distancebetween them is set to about 1000 Å in this embodiment. In the prior arttechnique, the extrinsic base polycrystalline SiGe film (as indicated byreference numeral 9 in FIG. 1) is set to about 100 to 150 Å inthickness, and the intrinsic base SiGe film is set to 500 Å inthickness, so that the intrinsic base is not connected to the extrinsicbase unless the distance between the base electrode silicon and thecollector epitaxial layer is set to about 600 Å or less. That is,according to this invention, the parasitic capacitance becomes600Å/1000Å=0.6 times as compared with the prior art technique. In orderto reduce the parasitic capacitance by the prior art technique, theintrinsic base must be thickened, and thus the cut-off frequency f_(T)is lowered.

Further, in this embodiment, the base electrode silicon is made ofsingle crystal, and thus the resistance of this portion is reduced.

Next, a third embodiment according to the present invention will bedescribed with reference to FIG. 6.

In this embodiment, the portion corresponding to the single crystalsilicon film 33 of the first embodiment is replaced by a dual-layerstructure of a TiSi₂ film 17 and a single crystal film 20. The otherstructure is identical to that of the first embodiment. With thisstructure, the base resistance can be more reduced because the TiSi₂film 17 has low resistance.

In the manufacturing process for the semiconductor device of thisembodiment, a Ti film is deposited on the single crystal silicon film 20by the sputtering method, and then subjected to the heat treatment toobtain the dual-layer structure as described above. For example, whenthe thickness of the TiSi₂ film 17 is about 1000 Å while the thicknessof the single crystal silicon film 20 is about 1500 Å and apredetermined wiring width is used, a sheet resistance ρ_(s) is equal to2 to 3Ω. This resistance value is equal to a half or less of theresistance value (8 to 9Ω) obtained when the thickness of the singlecrystal silicon film 33 is set to about 2500 Åand the same wiring widthis used.

In the present invention, a metallic silicide other than titaniumsilicide (TiSi₂) may be used.

FIG. 7 is a cross-sectional view showing a semiconductor device of afourth embodiment according to the present invention.

Referring to FIG. 7, the structure and the manufacturing process of thisembodiment is almost identical to those of the first embodiment, andthus only the different points between this embodiment and the firstembodiment will be described.

This embodiment is characterized by an emitter polycrystalline siliconfilm 21 doped with N-type impurities and an N⁺ -type emitter diffusionfilm 18. The intrinsic base film 39 is more thinned by a thicknesscorresponding to the N⁺ -type emitter diffusion film 18, so thatincrease of a switching speed of a transistor can be further promoted.In some cases, the contact surface between the base and the collector isslightly shifted to the collector side due to diffusion of impurities ofthe intrinsic base film into the epitaxial layer 3 when the emitterdiffusion film 18 is formed.

In this embodiment, the depth of the emitter diffusion film 18 is about200 Å, and thus the intrinsic base film 39 is formed by selectively andsuccessively growing Si₀.9 Ge₀.1 to a thickness of about 400 Å and thenSi to a thickness of about 200 Å to make the intrinsic base as a SiGealloy film. The boron concentration is about 6×10¹⁸ cm⁻³. As a result,the junction between the emitter and the collector is coincident withthe hetero junction of Si/Si₀.9 Ge₀.1, so that the improvement effect ofthe current gain h_(FE) can be kept. In this case, the extrinsic base 40also has a dual-layer structure of Si₀.9 Ge₀.1.

A fifth embodiment according to the present invention will be described.

This embodiment is characterized by an emitter single crystal siliconfilm 22 doped with N-type impurities of 1×10¹⁹ cm⁻³ and an emitterelectrode polycrystalline silicon film 19. The emitter electrodepolycrystalline silicon film 19 contributes to reduction of the basecurrent of a transistor, and thus it serves to improve the current gain.In addition, the silicon film 19 acts to prevent formation of an alloylayer between a wiring metal and the emitter single crystal silicon,which would be positioned in the neighborhood of the junction, in theheat treatment after the wiring metal is applied. Thus the destructionof the junction is hardly to occur.

As described above, according to the present invention, the baseelectrode silicon of single crystal is used, and thus the parasiticcapacitance between the base and the collector can be reduced in thetransistor in which the base is formed by the selective epitaxialgrowth, and particularly when SiGe is used for the base, the parasiticcapacitance can be reduced to about 60%.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising:a first step of forming a first insulation film on asurface of a first conduction type single crystal semiconductor layer; asecond step of forming on said first insulation film a first singlecrystal semiconductor film of a second conduction type through which afirst opening is selectively formed; a third step of forming a secondinsulation film on an upper surface of said first single crystalsemiconductor film and on a side surface of said first single crystalsemiconductor film which defines said first opening; a fourth step ofselectively removing said first insulation film using said secondinsulation film and said first single crystal semiconductor film as amask to form through said first insulation film a second opening whichis larger than said first opening; a fifth step of growing a secondsingle crystal semiconductor film of a second conduction type on anexposed surface of said first conductor type single crystalsemiconductor layer within said second opening and growing a thirdsingle crystal semiconductor film of a second conduction type on anexposed lower surface of said first single crystal semiconductor film sothat said second and third single crystal semiconductor films areconnected to each other, said second and third single crystalsemiconductor films being made of silicon-germanium; and a sixth step offorming a third insulation film between said second insulation film andsaid second single crystal semiconductor film so as to cover an exposedside surface of said third single crystal semiconductor film.
 2. Themethod for manufacturing a semiconductor device as set forth in claim 1,wherein said first conduction type single crystal semiconductor layerand said first single crystal semiconductor film are made of silicon,and said second and third single crystal semiconductor films are made ofsilicon-germanium.
 3. The method for manufacturing a semiconductordevice as set forth in claim 1, wherein said first and third insulationfilms are made of silicon oxide, and said second insulation film is madeof silicon nitride.
 4. The method for manufacturing a semiconductordevice as set forth in claim 1, wherein a metallic silicide film isformed on said first single crystal semiconductor film in said secondstep.
 5. The method for manufacturing a semiconductor device as setforth in claim 1, wherein a single crystal semiconductor of a firstconduction type is formed on the surface of a semiconductor substrate,an area of said single crystal semiconductor being used as said firstconduction type single crystal semiconductor layer, and, in said secondstep, after a third opening is formed through said first single crystalsemiconductor film at a portion corresponding to the other area of saidsingle crystal semiconductor, an amorphous semiconductor is deposited,then, by a solid phase epitaxial growth method using said single crystalsemiconductor at said other area in said third opening as a seedcrystal, said amorphous semiconductor is crystallized to a singlecrystal semiconductor, and then a patterning of said crystallized singlecrystal semiconductor is carried out to obtain said first single crystalsemiconductor film.
 6. The method for manufacturing a semiconductordevice as set forth in claim 1, further comprising a seventh step offorming a fourth single crystal semiconductor film of a first conductiontype on an exposed surface of said second single crystal semiconductorfilm after said sixth step.
 7. The method for manufacturing asemiconductor device as set forth in claim 6, wherein a polycrystallinesilicon film is formed on said fourth single crystal semiconductor filmin said seventh step.
 8. The method for manufacturing a semiconductordevice as set forth in claim 1, further comprising a eighth step offorming a polycrystalline silicon film of a first conduction type on anexposed surface of said second single crystal semiconductor film aftersaid sixth step and diffusing impurities of a first conduction type fromsaid polycrystalline silicon film to said second single crystalsemiconductor film by heat treatment to form a first conduction typeimpurity diffusion area.
 9. The method for manufacturing a semiconductordevice as set forth in claim 1, wherein said second and third singlecrystal semiconductor films are grown at the same time under the samecondition.